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SA1620 Low voltage GSM front-end transceiver
Product specification Supersedes data of 1996 Oct 08 IC17 Data Handbook 1997 May 22
Philips Semiconductors
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
DESCRIPTION
The SA1620 is a combined receive (Rx) and transmit (Tx) front-end for GSM cellular telephones. The receive path contains two low noise amplifiers (LNA1 and LNA2) with four switchable attenuation steps. A Gilbert Cell mixer in the receive path down-converts the RF signal to a first IF of 70 to 500 MHz. A second Gilbert Cell in the transmit path transposes a GMSK or phase modulated IF to RF by image reject mixing and has a fixed IF of 400 MHz. A buffered LO signal is fed to Rx and Tx mixers. Rx or Tx path or the entire circuit may be powered-down.
* Feedthrough attenuation LNA1 to Rx mixer 35dB * Tx power adjustable from -3 to +12dBm by external resistor * Direct supply: 2.7V to 5.5V * Battery supply voltage VBATT = 3.3V to 7.5V or direct supply * Two DC regulators programmable for 3.0V, 3.4V, 3.7V or 5.1V * Low current consumption: 28mA for Rx or 59mA for Tx * Fully compatible with SA1638 GSM IF Digital I/Q circuit
APPLICATIONS
FEATURES
* Excellent noise figure: <2dB for the LNAs at 950MHz * LNAs matched to 50 with external matching components * LNAs with gain control, 59dB dynamic range in four discrete steps * LNA gain stability 0.5dB within -40 to 85C
PIN CONFIGURATION
* 900MHz front end for GSM hand-held units * Portable radio, TDMA systems
LQFP Package
PONBUF 36 35 34 33 32 31 48-PIN LQFP 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 GNDBM RxIF TxIF GND1 RxIFX GND2 TxIFX GND3 VccTx1 PONRx GNDTx1 VccTx2 GNDL1A GNDTx3 GNDTx4 GNDL1 VccL1 OUT1 RETx PDTx Tx0X TxO IN1
48 47 46 45 44 43 42 VCCL2 IN2 GNDL2 GNDL2A OUT2 B A INM INMX COMP2 COMP1 VCCBM 1 2 3 4 5 6 7 8 9 10 11 12
41 40 39 38 37 VBATT PON GNDREG1 VREG1 VREGF2 VREG2 GNDREG2 CON1 LO INX LO IN CON2 GNDTx2
SR00127
Figure 1. Pin Configuration
ORDERING INFORMATION
DESCRIPTION 48-Pin Thin Quad Flat Pack (TQFP) TEMPERATURE RANGE -40 to +85C ORDER CODE SA1620BE DWG # SOT313-2
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCCXX VBATT TA Supply voltages Battery voltage Operating ambient temperature range PARAMETER RATING 2.7 to 5.5 3.3 to 7.5 -40 to +85 UNITS V V C
1997 May 22
2
853-1784 18066
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
BLOCK DIAGRAM
V CC BM
GNDTx1
GNDTx2
GNDTx3
GNDTx4
GNDBM
COMP1
COMP2
V BATT
GND1
GND2
GND3
CON1
PDTx PONRx PONBUF BANDGAP BIAS SUPPLIES
CON2
PON
VOLTAGE REGULATORS
VREG2 VREG2F2 GNDREG2 GNDREG1 VREG1
VCCTx1 VCCTx2 TxO TxOX SINGLE SIDEBAND MIXER LINEAR IF LEVEL CONTROL TxIF TxIFX
RETx TLO BUFFER A ATTENUATION B CONTROL LOGIC BUFFER TLOX LO INPUT BUFFER LO IN LO INX
VCCL1 VCCL2
RLOX
RLO
RxIF IN1 LNA1 LNA2 RxIFX
GNDL1A
GNDL2A
INM
GNDL1
OUT1
GNDL2
IN2
OUT2
INMX
SR00129
Figure 2. Block Diagram
1997 May 22
3
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
PIN DESCRIPTIONS
Pin No. Pin Name Description Pin No. 13 Ground of regulator supply Ground of regulator supply Ground of regulator supply Control 2, voltage select for regulator 1 and 2 Control 1, voltage select for regulator 1 and 2 Ground of regulator 2 Output of regulator 2 Feedback of regulator 2 Output of regulator 1 Ground of regulator 1 Power-on input of regulators Input of regulator 1 and 2 14 16 17 44 45 46 47 48 Tx Path 19 20 22 23 24 VCCL2 IN2 GNDL2 GNDL2A OUT2 B A INM INMX COMP2 COMP1 VCCBM Positive supply for LNA2 Input LNA2 Ground L2 for LNA2 Ground L2A for LNA2 Output LNA2 Attenuation select B for LNA1 and LNA2 Attenuation select A for LNA1 and LNA2 RF input for Rx mixer, open emitter Inverse RF input for Rx mixer, open emitter Capacitor for bias stabilization Capacitor for bias stabilization VCC for Rx Bias and Rx mixer 25 38 39 40 41 42 43 TxIF TxIFX VCCTx1 GNDTx1 VCCTx2 GNDTx2 PDTx GNDTx4 TxOX TxO GNDTx3 RETx IF input for Tx Inverse IF input for Tx Positive supply for Tx input Ground for Tx input Positive supply for LO and Tx input Ground for LO and Tx input Power down Tx input Ground for Tx output Inverse Tx output, open collector Tx output, open collector Ground 1 for Tx output side Reference resistor for Tx output current Pin Name GNDBM PONRx RxIF RxIFX IN1 GNDL1 GNDL1A OUT1 VCCL1 Description Ground for Rx Bias and Rx mixer Power on input for Rx bias supply IF output, open collector Inverse IF output, open collector Input to LNA1 Ground L1 for LNA1 Ground L1A for LNA1 Output LNA1 Positive supply for LNA1 DC Regulators 15 18 21 26 29 30 31 32 33 34 35 36 Rx Path 1 2 3 4 5 6 7 8 9 10 11 12 GND1 GND2 GND3 CON2 CON1 GNDREG2 VREG2 VREG2F2 VREG1 GNDREG1 PON VBATT
Elements for Tx and Rx Path 27 28 37 LO IN LO INX PONBUF Input for Local Oscillator signal Inverse input for LO or AC ground Power on first stage LO input buffer and bias
NOTES: 1. Device is ESD sensitive. There are no ESD protection diodes at Pins 16, 17, 40 and 41. Thus, open-collector outputs may have increased DC voltage or higher AC peak voltage. 2. Pins 15, 18 and 21 are connected to each other and to a separate ground in REG1 and REG2. 3. Pins 23, 25, 42 and 39 are connected to each other and to the Tx path, LO buffer and associated bias supplies. 4. Pins 22 and 24 are connected to each other providing a sense input. They are also connected to the Tx path, LO buffer and associated bias supplies. 5. Pins 30 and 34 are not internally connected. They must be connected to external grounds. 6. Pins 48, 1, and 12 are not internally connected and have no ESD protection diodes between them. Power may be saved by connecting VCCL1 and IN1 or VCCL2 and IN2 to ground if LNA1 or LNA2 is not needed.
1997 May 22
4
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCCXX VBATT VIN V VG PD TJMAX PMAX TSTG VTXO, VTXOX VRXIF, VRXIFX Supply voltages Battery voltage Voltage applied to any other pin VCCTx1,2 pins to VCCBM Any GND pin to any other GND pin Power dissipation, TA = 25C (still air) Maximum operating junction temperature Maximum power input/output Storage temperature range Positive RF peak voltage at Tx outputs Positive IF peak voltage at Rx mixer outputs PARAMETER RATING -0.3 to +6.0 -0.3 to +8.0 -0.3 to (VCCXX+0.3) -0.3 to +1 0 800 150 +20 -65 to +150 6 6 UNITS V V V V V mW C dBm C V V
NOTE: 1. Maximum junction temperature is determined by the power dissipation is determined by the operating ambient temperature and the thermal resistance, JA. 48-pin TQFP: JA = 67C/W.
DC REGULATORS
Two low drop regulators (REG1 and REG2) are included on the chip and may be used to deliver the supply voltage of the main circuitry (e.g., 3V) out of the battery (at VBATT = 3.3 to 7.5V) as shown in Figure 4 and in Table 1. REG1 is intended to supply, at least, the internal functions of the SA1620. Both regulators may also be used for external circuitry. For this application, different voltages may be programmed as shown in Table 1. The transmitter supply pins (VCCTx1,2) also operate as a sensor connection in the feedback loop of REG1 and must be externally connected to pin VREG1. For REG2, the sensor pin VREGF2 must be connected to VREG2. All ground pins are internally bonded to the header except for pins GNDL1, GNDREG1 and GNDREG2. When both regulators are not used, connect pins VBATT, PON, CON1, CON2, VREG1, VREG2 and VREG2F2 to ground.
Table 1. DC Reg Output Voltage Control Pins
CON1 L L H H CON2 L H L H VREG1 3 5% 3.4 5% 3.7 5% 5.1 5% VREG2 3 5% 3.4 5% 3.7 5% 5.1 10% UNITS V V V V
NOTES: 1. Logic levels at CON1 and CON2: H - Open circuit. Pin must not be connected externally. Logic high level supplied on chip. L - Connected to ground. 2. Currents at CON1 and CON2: H - 0A L (PON = H) - 50A L (PON = L) - <1A
1997 May 22
5
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 2. DC Regulators
SYMBOL VBATT VREG1, VREG2 IINT1 IINT2 IINT01, IINT02 IVREG1MAX5 IVREG2MAX5 BW6 PARAMETER Common positive input voltage at both regulators Output voltages of regulators 1 and 2 Internal current of REG1 in power-on mode Internal current of REG2 in power-on mode Internal current in power-down mode Max output current at VREG1 Max output current at VREG2 VBATT = 3.3V, IREG1 = 0.1mA VBATT = 3.3V, IREG1 = 100mA VBATT = 7.5V, IREG1 = 100mA 100kHz FREG7 G 10MHz f 100MHz 400MHz 0.03 60 80 -61 -32 -37 -48 dB kHz VBATT = 3.3V TEST CONDITIONS LIMITS MIN VREG1+0.3 2.85 3 4 + IVREG1/10 2.5 + IVREG2/10 <15 100 30 3.15 TYP MAX UNITS V V mA mA A mA mA
NOTES: 1. Power-on pin of Regulator 1 and 2: PON 2. Input currents at PON: <1A. There are no pull-up or pull-down resistors. 3. Feedthrough attenuation from the logic input PON to the outputs VREG1 and VREG2: 40dB. 4. Recommended load capacitors: C529 = C530 = 1F to ground with series resistance 0.1. See Figure 4. Additional optional capacitor 1000F with series resistance 5. 5. At Tj 150C a thermal switch reduces the output current. 6. Typical open loop bandwidths of regulator 1 at VREG1 = 3V and C529 = 1F. 7. Feedthrough attenuation (at the indicated frequency f) from the input VBATT to the outputs VREG1 and VREG2 at VBATT = 3.3V, (CON1=CON2=L)
1997 May 22
6
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
DC ELECTRICAL CHARACTERISTICS
VCCxxx = +3V, TA = 25C; unless otherwise stated. LIMITS SYMBOL Transmitter IVCC R1 VR1 Total supply current External resistor1 Internal supply at pin RETx VCCTx1,2 = 2.7V VCCTx1,2 = 5.5V R546 = 240, VCCTx1,2 = 2.7V R546 = 240, VCCTx1,2 = 5.5V G1hi mode G2hi mode 2.5 2.5 Transmit mode R546 = 240 59 240 0.43 0.45 1.7 1.8 mA V 90 mA PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
IR1
Current at pin RETx
Low noise amplifiers IVCCL1 IVCCL2 Receiver IVCC Regulators Vreg1 Voltage @ 100mA load Con1 L L H H Vreg2 Voltage @ 30mA load Con1 L L H H Logic levels2 Logic 1 level Logic 1 level Logic 0 level Input logic current Input logic capacitance 1.7 PONBUF, PDTx, PONRx, A, B PON 2.0 2.0 0 VCCBM3 VBATT 0.8 1 V V V A pF Con2 L H L H Con2 L H L H 2.85 3.23 3.515 4.61 3.0 3.4 3.7 5.1 3.15 3.57 3.885 5.61 V V V V 2.85 3.23 3.515 4.61 3.0 3.4 3.7 5.1 3.15 3.57 3.885 5.61 V V V V Total supply current Receive mode R546 = 240 28 39 mA Current at pin VCCL1 Current at pin VCCL2 3.5 3.5 5 5 mA mA
VIH VIH VIL II CIa
NOTES: 1. The output current ITXO + ITXOX is adjustable by the external resistor R546. ITXO + ITXOX = 10 * IR546, IR546 = VR1/R546, 2. Thresholds are independent of supply voltages. Thus the SA1620 is compatible with SA1638 and with the power down inputs of usual external voltage regulators. 3. PON logic 1 max is VBATT.
1997 May 22
7
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
AC ELECTRICAL CHARACTERISTICS
VCCXX = +3V, TA = 25C; RF = 940MHZ; IF=400MHz, fLO=RF + IF; LO = -15dBm; unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS LIMITS1 MIN1 -3 9.4 -13 TYP 10 -2.5 -12 28 0.003 0.0140 0.1 0.01 G1hi mode 50 50 G1hi mode -15.5 -5.5 -19 -11 -14 -14 -4 0.011 1.9 7 0.5 -12.5 -2.5 dB/C dB/V dB/MHz dB dB dB dBm dBm dB/C dB s s 11 -6.5 -20.5 -27 dB dB dB -11 3 10.6 dB MAX1 UNITS
Low Noise Amplifier LNA12 G1hi mode S21 Gain IP3 S21/T S21/ VCCL1 S21/f S12 S11 S22 P-1dB IIP3 IIP3/t NF tON tOFF Gain temperature sensitivity Gain/voltage sensitivity Gain frequency variation Reverse isolation Input match3 Output match3 G1hi mode, RF = 1800MHz G1lo mode G1lo mode G1hi mode G1lo mode
Input 1dB gain compression Input third order intercept Input third order intercept Noise figure Turn-on time Turn-off time
Low Noise Amplifier LNA22 G2hi mode G2hi mode, RF = 1800MHz Gain S21 G2lo1 mode G2lo2 mode G2lo3 mode G2lo1 mode IP3 G2lo2 mode G2lo3 mode S21/T S21/ VCCL2 S21/f S12 S11 S22 P-1dB IIP3 IIP3/t NF tON tOFF Gain temperature sensitivity Gain/voltage sensitivity Gain frequency variation Reverse isolation Input match3 Output match3 Input 1dB gain compression Input third order intercept Input third order intercept Noise figure Turn-on time Turn-off time G2hi mode 50 50 G2hi mode -18 -8 G2hi mode G2lo1,2,3 modes -8.5 -22.5 -30 9 10 -1.5 -7.5 -21.5 -28.5 18 20 25 0.003 0.014 0.1 0.01 -24 -13 -15 -16 -6 0.019 2 7 0.5 -14 -4 dB/C dB/V dB/MHz dB dB dB dBm dBm dB/C dB s s
1997 May 22
8
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
AC ELECTRICAL CHARACTERISTICS (continued)
SYMBOL Rx Mixer PGC S11 NFM P-1dB IIP3 IIP3/t IIP2 GRFM-IF GLOfloor GLO-IF GLO-RFM GLO-RF1 GLNA1-2 GLNA2-M GLNA1-M Receiver 6 Cascaded gain A,B Logic Level H,H H,L L,H L,L Input IP3 @ RFin=-40dBm LO input ZIN PIN ASAT Tx IF input |ZIN| PIN Input impedance Input power R546 = 240, VCCTx1,2 = 3V 400MHz 2 -20 k dBm Input impedance (each single-ended input) Input power Transistor saturation limit, max input amplitude 1.3GHz -257 35-j97 -15 500 dBm mV H,H 23.5 6 -8 -41 26.5 9 -5 -36 -20 28.5 11 -3 -32 -18 30.5 13 -1 +28 -16 33.5 16 +2 -23 dB dB dB dB dBm Power conversion gain5 Mixer input match at ports INM and INMX4 SSB combined noise figure Input 1dB compression Input third order intercept Input third order intercept Input second order intercept RF feedthrough LO floor feedthrough LO feedthrough to IF LO to mixer input feedthrough LO to RF LNA1 input feedthrough LNA1 output to LNA2 input feedthrough LNA2 output to mixer input feedthrough LNA1 output to mixer input feedthrough 400MHz 400MHz 1.3GHz 1.3GHz 1.3GHz 400MHz 1290-1760MHz 1290-1760MHz 400MHz 1290-1760MHz 0 7.5 RF = 1800MHz +8.5 -4 -13 10 -7.3 2 0.005 19 -26 -30 -16 -50 -65 -41 -26 -23 -50 -35 4 9.5 dB dB dB dBm dBm dB/C dBm dB dB dB dBm dBm dB dB dB PARAMETER TEST CONDITIONS LIMITS1 MIN1 -3 TYP 3 MAX1 UNITS
Tx RF output POUT 5 7.5 8.5 9.5 dBm
NOTES: 1. Due to our automatic test equipment accuracy and repeatability test limits may not reflect the ultimate device performance. Standard deviations are calculated from characterization data. 2. If the LNA1 is not needed, connect pin VCCL1 and IN1 to GND. If the LNA2 is not needed, connect pin VCCL2 and IN2 to GND. 3. Simple L/C elements are needed to achieve specified return loss. 4. The mixer RF inputs (emitters of a Gilbert Cell) may be driven by a symmetrical matching network. 5. Input symmetry suppression is such that the product 6*RF-4*LO is to be suppressed by at least 66dB relative to the wanted IF output when the input to the mixer is at -32dBm. 6. LNA1, LNA2, and the mixer are cascaded. 0 db insertion loss between LNA1 out to LNA2 in and LNA2 out to mixer in. 7. Lowering the LO input power (PIN) from TYP to MIN will lower the mixer gain (PGC) by 1 dB. 1997 May 22 9
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 3. Power-Down and Tx/Rx Control Logic
No. 1 2 3 4 5 PONBUF H H H H L PDTX H L H L x PONRX L L H H x MODE Standby Transmit Receive Calibrate Power-Down RESULT LO buffer active, Tx and Rx path inactive LO buffer active, Tx path active, Rx path inactive (LNAs + mixer) Tx path inactive, LO buffer and Rx path active (LNAs + mixer) Tx path and Rx LNAs inactive, LO buffer and Rx mixer active Tx- and Rx-path, LO buffers and Bias inactive
NOTES: 1. Logic levels of PONBUF, PDTx and PONRx: TTL, see DC Electrical Characteristics. 2. Logic levels / polarities are compatible with Philips Semiconductors Power Amp Controller PCA5075 and synthesizers UMA1019 or SA8025. 3. First stage of LO buffer and parts of bias supply are powered on by PONBUF. 4. Tx- or Rx-paths may be activated for special timeslots. Lines 1 and 4 show options to support DC offset calibrations at baseband mixers, following in the receiver chain (SA1638).
Table 4. Gain Control Logic for LNA1 and LNA2
INPUT a H H L L b H L H L ATTENUATION STEP 0 1 2 3 GAIN LNA1 G1hi G1hi G1hi G1lo LNA2 G2hi G2lo1 G2lo2 G2lo3 POWER CONSUMPTION LNA1 on on on off LNA2 on off off off
NOTES: 1. Logic levels of a and b: TTL 2. For values of G1hi and G1lo, G2hi, G2lo1, G2lo2 and G2lo3 see LNA1 and LNA2 AC Electrical Characteristics.
1997 May 22
10
1997 May 22
INTERFACE TO MICROCONTROLLER
Philips Semiconductors
PCA5075 SERIAL POWER AMP INPUT CONTROLLER
SA1620 SA1638
400MHz SSB MIXER LINEAR IF LEVEL CONTROL
I I Q
PA
BUFFER POWER SUPPLY Tx/Rx 400MHz
LO1 (1290-1360MHz)
Q I I Q
Tx: 935-960MHz ATTENUATION CONTROL LOGIC SAW LO2 800MHz
A
Low voltage GSM front-end transceiver
B
Q
Figure 3.
11
PD PD LNA2 FREQUENCY SYNTHESIZER (SA8025, UMA1019) LNA1
Rx: 890-915MHz
/ / /
CLKIN 13MHz AOUT BOUT (to SA1620 ATTENUATION CONTROL LOGIC INPUTS)
INTERFACE TO MICROCONTROLLER
SA1620
Product specification
SR00130
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Overview of Dual GSM/PCN Architecture
The SA1620 RF front-end and SA1638 IF transceivers form a dual conversion architecture which uses a common IF and standard I/Q baseband interface for both transmit and receive paths. This approach avoids the screening difficulties of direct modulation in the transmit direction and the mass production and practical performance issues related to direct conversion in the receive direction. The time division multiplex nature of the GSM system permits integration of the transmit and receive functions together on the one RF and one IF chips. This simplifies the distribution of local oscillator signals, maximizes circuitry commonality, and reduces power consumption. The SA1620 and SA1638 allow considerable flexibility to optimize the transceiver design for particular price/size/performance requirements, through choice of appropriate RF and IF filters. The receive IF may be chosen freely in the range 70-500MHz, while the transmit IF is fixed to 400 MHz. The comparison frequency of the SA1638 PLL is high in order to provide fast switching time. With suitable choice of the IF, an identical SA1638 IF receiver design can be used for both 900MHz GSM and 1800MHz PCN (DCS1800) equipment.
Receive Path
Multiple LNAs allow the flexibility to exploit the best choice of currently available filters (on performance, size, or cost grounds). This approach is preferable to a single high-gain stage as the stray cross-coupling effects between pins remain manageable. In a single stage amplifier this would limit the amount of rejection of out-of-band signals that could be achieved, and would also limit the amount of AGC attenuation that could be practically implemented. The LNAs are powered up only when PONBUF, PDTx and PONRx are high, to allow a high degree of battery economy. If greater sensitivity is required for an application, an external preamplifier circuit can be used instead of LNA1, and LNA1 left unconnected. A special mode is provided with just the IF output related circuitry active in order to allow calibration of the DC offset at the SA1638 baseband receive outputs. This offset contains a contribution due to coupling effects between the second local oscillator and the IF circuitry, and therefore the receiver is set up in the receive state (but with incoming signals excluded) to allow accurate offset calibration.
Gain Control
Gain control is implemented in the SA1620 RF front-end. This avoids the disruption of the DC offset at the baseband IQ outputs that is typically caused by changes in the AGC. The SA1620 and SA1638 are designed so that the GSM dynamic range requirements can be met with the AGC remaining on the maximum gain setting. These gain steps scale the dynamic range of the received signal (e.g., 90dB for GSM) into the dynamic range of the baseband processing device. The absolute gain tolerances may be measured together with the attenuation tolerances of external filters during production of the receiver equipment. After software calibration switching from one dynamic range to another will cause only minor errors.
General Benefits/Advantages
* 2.7V operation.
Compatible with 3V digital technology and portable applications. (Higher voltage operation also possible, if desired.) The availability of two LNAs allows flexibility in receiver dynamic design for portable and mobile GSM spec. applications with appropriate filters. If for a particular application a GaAs or discrete front-end is desired, one of the LNAs can be left unpowered. The placing of the AGC gains switches at the front means that for most of the time some attenuation will be inserted, further increasing typical dynamic performance beyond that specified by GSM. This is sufficient to drive a filter and power amplifier input, without a driver amplifier. To avoid unnecessary current consumption the output power can be reduced, if not required, by appropriate choice of an external resistor.
* Excellent dynamic range.
* High power transmit output driver, delivering +8.5dBm output.
Tx Path
TXIF and TXIFX are differential IF inputs for phase modulated signals (e.g., GMSK). There is an IF level control loop which provides a constant amplitude to an image reject up mixer. Thus, this mixer operates linearly in the IF path, independent of IF level tolerances. The single sideband up mixer is sufficient in quadrature to achieve the typical performance indicated in Table 6 over an IF range of 250 to 500MHz. The mixer is operating in switching mode by well matched 0 and 90 LO signals, optimized for 1.1 to 1.5GHz. The Tx output stage operates in switching mode. Thus, parasitic AM at the IF is not transferred. The outputs TXO and TXOX may be used symmetrically or single-ended. Some spurious emissions will be very low when a symmetrical output signal is used. POUT = R e 6.25V @ (Z Pin 40 ) Z Pin 41) @ (I R546) 2 V R546 according to DC Electrical R 546 Characteristics. POUT is adjustable with R546 and is accurate to within 1dB over the full voltage range 2.7 to 5.5V, and 0.5dB from a given supply voltage. The absolute limit of the negative peak voltage swing at pins TxO and TxOX is VSAT = VCCTx1,2 - 1V. The absolute limit of the positive peak voltage is +6V. according to Figure 4 and I R546 +
* DC offsets generated in the receive channel are independent of
the AGC setting, and correctable by software to prevent erosion of signal handling dynamic range by DC offsets. Independence of DC from AGC setting is achieved by putting the gain switches in the RF front-end.
* Minimal high-quality filter requirements.
As a result of the integration in the SA1638 of high quality channel selectivity filters, only sufficient filtering is needed in the receive path to provide blocking protection for the second mixers. This reduces receiver cost and size. For example, at a 400MHz IF, the natural gain roll-off in the LNAs and mixer suppresses the image signal in the 1800MHz band by typically 28dB below the desired 900MHz band signal.
* Operation at a high IF allows RF image reject filters to be relaxed.
1997 May 22
12
690
335
605
940
C533 c=33p 335
C650 c=33p r=240 R546
Vcc/Gnd
Vcc/Gnd
IN1
TxO
RETx
VccL1
OUT1
GNDL1
GNDTx3
TxOX
GNDL1A
GNDTx4
PDTx
PONBUF
180
420
GNDBM
PONRx
GND1
RxIF
RxIFX
GND2
TxIF
TxIFX
GDN3
VccTx1
GNDTx1
350
350
350
C618 c=8.2p C623 c=10p
350
Vcc/Gnd
C626
c=3.3p
C622 c=10p
C615 c=10p o o L617 I=22n I=22n C620 c=3.3p L624 o L627 I=56n C539 c=33p
VccTx2
1997 May 22
LNA_In o TMXR_Out C613 c=33p V503 vdc=7.5
-+ C610 c=3.9p I=56n L612
LNA1_Out C574 c=33p r=100 R651
C573 c:1p C609 c=3.9p
Philips Semiconductors
C575 c=33p
C611 c=33p
Vbatt C635 c-100n
C534 c=33p C527 c=100n c=10u C636 Vbatt/Gnd 890 IN2 PON GNDREG1 Vcc GNDL2A VREG1 VREGF2 xxx VRegF2 C=1u C529 (ceramic!!!) 650 OUT2 B A INM INMX COMP1 COMP2 VCCBM Vcc/Gnd GNDL2 C528 c=100n
C339 c=1n
VCCL2 VBATT
LNA2_In
o
L648 I=56n
C336
LNA2_Out
Low voltage GSM front-end transceiver
RMXR_In
c=33p
10 mils wide, xxx mils long on 31 mils thick FR4 substrate.
VREG2 GNDREG2 CON1
Figure 4. Application Circuit
13
Vcc/Gnd 340 340
C644 c=33p
C530 c=1u (ceramic!!!)
Open/Gnd LOINX
C565 c=33p
C631 c=4.7p
LO_In LOIN CON2 Open/Gnd GNDTx2 C564 C=33p
R641 r=100
SA 1620
8/12/96
C643 c=33p
c=10n C380 c=10n C645
C535 c=100n
gnd
RMXR+Out C619 c=33p
C628 c=100n
TMXR_In
Product specification
SA1620
SR01332
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
APPLICATION CIRCUIT LNA
Impedance Match: Intrinsic return losses at the input and output ports are 7dB and 11dB, respectively. However, since long and narrow traces are always needed to fan out the pins, the user can adjust the traces' dimensions so that only one shunt capacitor at the input is required to achieve excellent impedance match for both ports. If the user wants to skip the input matching network for simplicity, then roughly 0.7dB gain would be lost, although it benefits the system IP3. Noise Match: The LNA1 and LNA2 can achieve 1.9dB and 2.0dB noise figure, respectively, when S11 = -11dB. Further improvement in S11 will slightly decrease NF and increase S21. Gain Control: The LNA1 can be switched to the attenuation mode, while LNA2 has three attenuation modes to choose from. When gain and loss modes from two LNAs are combined, there will be a total dynamic range of 59dB in the RF block; 3.0V operation is preferred to achieve better IP3 for both LNA1 and LNA2. Temperature Compensation: Both LNAs have a built-in temperature compensation scheme to reduce the gain drift rate to 0.003dB/C from -40C to +85C. Supply Voltage Compensation: Unique circuitry provides gain stabilization over wide supply voltage range. The gain changes no more than 0.5dB when VCC increases from 2.7V to 5.5V.
recommended to be the receiver band plus 400MHz. Additionally, the LO leakage at the input of LNA1 is extremely low, which can greatly alleviate the LO re-radiation problem. Outband Blocking: For optimum performance, passive R/C network is added at each input of the mixer. The resistors degenerate the noise conversion gain, while the capacitors preserve the gain and noise figure at RF frequencies. Noise Figure and IP3: The resonant balun is superior to the conventional balun in terms of insertion loss, size and cost. As a result, the user can expect excellent SSB noise figure and gain which is 10dB and 8.5dB, respectively, at 400MHz IF. And the associated input IP3 is 2dBm typically. In the meantime, due to the internal LO buffer, the noise figure and IP3 are not sensitive to the LO levels. As discussed in the LNA Impedance Match session, a better system IP3 can be achieved (if necessary) through LNAs' gain reduction.
Transmitter
The resonant balun is applied again to maximize the gain and output power, for a given bias current. Typical output power is 8.5dBm when the input level exceeds -25dBm.
LO Input
The LO input is used in Tx- and in Rx-mode. Only one synthesizer PLL is necessary to supply the LO input with different frequencies in Tx and Rx timeslots. The LO input buffer should only be set in power-down mode together with the PLL. As further buffering is included on chip there will be no influence on the PLL in active mode when the SA1620 Rxor Tx-path is power On or Off. Current consumption can thus be saved by powering on the Rx- and Tx-circuitry just before it is required, without disruption of the LO circuitry. LO input pins LO IN and LO INX may be used single-ended or symmetrically.
Mixer
Mixer Input Match: The mixer is configured for best gain, noise figure and spurious response. The user must supply an external, patented resonant balun to provide the differential drive as well as the impedance match (embedded in). Because the mixer consists of two single-balance mixers, whose inputs are connected in parallel instead of in series, the differential and common-mode impedances are equal. Output Match: The mixer output circuit also features an external, patented resonant balun to optimize the conversion gain and noise figure. The principal IF operating frequency is 400 MHz. LO Drive: The internal buffer only requires -15dBm from an external source. Furthermore, the transmitter incorporates an integrated SSB upconverter that consists of narrowband phase shifters at 1300MHz (LO side) and 400MHz (IF side), so the LO frequency is
Table 5. GSM/DSC1800 Frequency Specification
(GSM 05.05, Version 4.2.0, April 1992) Mobile Stations Frequency Bands GSM Tx Rx 890 to 915 935 to 960 EGSM 880.2 to 915 925.2 to 960 DCS1800 1710 to 1785 1805 to 1880 Unit MHz MHz
1997 May 22
14
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 6. Measured Tx Output Frequency and Tx Mixer Products
IF=400MHz, symmetrical load at pins TxO, TxOX. SPECTRAL LINE f=n*IF+m*LO MHz No. LO = 1280MHz 80 160 320 400 480 560 720 800 880 960 1020 1200 1280 1360 1440 1600 1680 1760 1840 2000 2080 2160 2240 2400 2480 2560 LO = 1300MHz 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 LO = 1315MHz 115 230 285 400 515 630 685 800 915 1030 1185 1200 1315 1430 1545 1600 1715 1830 1945 2000 2115 2230 2345 2400 2515 2630 Order n -3 -6 4 1 -2 -5 5 2 -1 -4 6 3 0 -3 -6 4 1 -2 -5 5 2 -1 -4 6 3 0 m 1 2 -1 0 1 2 -1 0 1 2 -1 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 RELATIVE POWER OF SPECTRAL LINE min dBc typ dBc -70 -76 -60 -46 -31 -62 -56 -37 0 -46 -63 -60 -32 -46 -64 -75 -50 -34 -68 -77 -74 -67 -59 -75 -76 -70 2LO Notes 4 and 5 Note 3 Note 3 LO Note 2 Note 1 Note 3 IF max dBc
REMARKS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
NOTES: 1. Desired Tx output frequency LO-IF corresponding to EGSM Tx band in Table 5. 2. (LO+IF)-(LO-IF) = 2 * IF 3. See Rx bands in Table 5. 4. LO+IF = mixer image frequency 5. See Tx bands in Table 5.
1997 May 22
15
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 7. Measured Tx Output Noise Floor
dBc/Hz Freq ency MHz Frequency < 860 860 to 880 880.2 to 890 890 to 915 915 to 925 925.2 to 935 935 to 960 960 to 1000 1000 to 1710 1710 to 1785 1785 to 1805 1805 to 1880 1880 to 12750 Adjacent Channel MIN TYP -135 -134 -133 -133 -133 -134 -135 -135 -135 -146 -145 -144 -147 -130 DCS1800 RX DCS1800 TX EGSM RX extension GSM RX EGSM TX extension GSM TX MAX REMARKS
1997 May 22
16
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
5 4.5 Icc (mA) Icc (mA) 4 3.5 3 2.5 2 -40 25 Temp (C) 85 3V
40 35 30 25 20 15 3V 4V 5V
4V 5V
-40
25 Temp (C)
85
SR01334
SR01333
Figure 5. LNA1_ICC vs. Temp
Figure 8. Receive ICC vs. Temp
5 4.5 Icc (mA) 4 3.5 3 2.5 2 -40 25 Temp (C) 85 3V
10 9 5V Icc (mA) 4V 5V 8 7 6 5 4 -40 25 Temp (C) 85 3V 4V
SR01339
SR01338
Figure 6. LNA_2 ICC vs. Temp
Figure 9. Standby_ICC vs. Temp
70 65 Icc (mA) 60 55 50 45 40 -40 25 Temp (C) 85 3V 5V 4V Icc (mA)
28 26 24 22 20 18 16 14 12 10 -40
3V 4V 5V
25 Temp (C)
85
SR01344
SR01337
Figure 7. Transmit_ICC vs. Temp
Figure 10. Calibrate_ICC vs. Temp
1997 May 22
17
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
34 32 GAIN (dB) 30 GAIN (dB) 28 26 24 22 20 -40 25 Temp (C) 85 4V 5V 3V
-20 -22 -24 -26 -28 -30 -32 -34 -36 -40 5V 25 Temp (C) 85 3V 4V
SR01342
SR01336
Figure 11. Receive_Gain Mode1 vs. Temp
Figure 14. Receive_Gain_Mode4 vs. Temp
15 13 3V GAIN (dB) 4V 9 5V 7 5 -40 25 Temp (C) 85 IP3 (dBm) 11
-15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -40
5V 4V 3V
SR01335
25 Temp (C)
85
SR01343
Figure 12. Receive_Gain_Mode2 vs. Temp
Figure 15. Receive IIP3 vs. Temp
0 -1 GAIN (dB) -2 5V -3 -4 -5 -6 -40 25 Temp (C) 85 SR01341 3V 4V
Figure 13. Receive_Gain_Mode3 vs. Temp
1997 May 22
18
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
2.0
10.80
1.9 5.0V NOISE FIGURE (dB)
3.0V NOISE FIGURE (dB) 10.40 2.7V 10.00
3.0V
1.8
2.7V
5.5V
5.0V
5.5V 9.60
1.7
1.6 -40
0
25 TEMPERATURE (C)
85
9.20 -40
0
25
85
TEMPERATURE (C)
SR00134
SR00140
Figure 16. Receive LNA1 Noise Figure
Figure 18. Receive Mixer Noise Figure
10.00 2.50
2.30 5.5V POWER (dBm) 5.0V 2.10 3.0V NOISE FIGURE (dB) 1.90 2.7V
9.00
5.5V 8.00 3.0V 5.0V 2.7V 7.00
1.70
1.50 -40
0
25
85
6.00 -40
0
TEMPERATURE (C)
25 TEMPERATURE (C)
85
SR00137
SR00149
Figure 17. Receive LNA2 Noise Figure
Figure 19. Transmit Power @ -25dBm
12 11 POWER (dBm) 10 9 8 7 6 5 4 -40 25 Temp (C) 85 5V 4V 3V
SR01345
Figure 20. Transmit_Power @ -20 dBm Input
1997 May 22
19
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
3.02 9.50
3.01 9.00 POWER (dBm) 5.0V 8.50 2.7V 8.00 3.0V 5.5V 3.00 Vreg (Volts) 0 -40
2.99
25
7.50
2.98
85
7.00 -40
2.97 0 25 TEMPERATURE (C) 85 0 3 6 15 18 21 9 12 FORCED CURRENT (mA) 24 27 30
SR00150
SR00153
Figure 21. Transmit Power @ -15dBm
Figure 24. Regulator 2 Load Regulation (VBATT = 3.5V)
3.01
9.00 3.00 5.5V 8.50 POWER (dBm) 5.0V 8.00 2.7V 3.0V 2.99 0 2.98 Vreg (Volts) 25 2.97 85 2.96 2.95 2.94 7.00 -25.00 2.93 3.3
-40
7.50
-20.00 INPUT POWER (dBm)
-15.00
3.5
4.5
5.5
6.5
7.5
FORCED CURRENT (mA)
SR00151
SR00154
Figure 22. Transmit Power @ 25C
Figure 25. Regulator 1 Line Regulation @ 100mA Load
3.01 -40 -40 0 Vreg (Volts) 3.00 0 2.98 25 Vreg (Volts) 2.99
25
85
2.98 85 2.97
2.93 0 10 20 30 40 50 60 70 80 90 100 2.96 3.3 3.5 4.5 5.5 6.5 7.5
FORCED CURRENT (mA)
FORCED CURRENT (mA)
SR00152
SR00155
Figure 23. Regulator 1 Load Regulation (VBATT = 3.5V)
Figure 26. Regulator 2 Line Regulation @ 30mA Load
1997 May 22
20
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
12 TRANSMITTER POWER (dBm) 10 8 6 4 2 0 -2 130 150 180 220 240 270 300 330 360 430 510 560 620 750 820 910 1000 -4 VCC = 3V Temp = 25C
100 90 80 CURRENT (mA) 70 60 50 40 30 130 150 180 220 240 270 300 330 360 430 510 560 620 750 820 910 1000 20 VCC = 3V Temp = 25C
R546 ()
R546 ()
SR00156
SR00157
Figure 27. Transmit Output Power vs R(546) @ VCC = 3V
Figure 28. Transmit Mode Current vs R(546) @ VCC = 3V
1997 May 22
21
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
PIN FUNCTIONS
PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT
1
PIN PIN DC V No. MNEMONIC
12
EQUIVALENT CIRCUIT
1
VCC
3.0
12
VCCBM
3.0
13 2 IN2 0.8
2
GND
0.0
POnRx 14 3 4 GNDL2 GNDL2a 0.0 0.0 15
5
-- 14 +
CMOS INPUT
GND
0.0
16 17
5
OUT2
2.2
16
Rxif
3.0
17 B 6 CMOS INPUT
6
RxifX
3.0
-- +
18
GND
0.0
19
Txif
2.2
19 20
A 7 CMOS INPUT
7
-- +
20
TxifX
2.2
21
GND
0.0
22
22 8 INM 0.4
8
VCCTx
3.0
23
GND
0.0
24
24 9 INMX 0.4
9
VCCTx
3.0
25 10 COMP2 2.2
10 or 11
GND
0.0
CON2 26 CMOS INPUT
26
-- +
11
COMP1
2.2
SR00162
Figure 29. Pin Functions
1997 May 22
22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
PIN FUNCTIONS (continued)
PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT
27
LOin
2.2 37
27 28
POnBuf CMOS INPUT
-- 37 +
28
LOinX
2.2 PDTx 38 CMOS INPUT
38 -- +
CON1 29 CMOS INPUT
29
-- +
39 30 GndReg1 0.0
VBATT --
GndTx TxOx
0.0
40 41
40
3.0
31
VReg2
3.0
41
31
TxO
3.0
+
42
GndReg2 32 VBATT
GndTx
0.0
43
RETx
0.4
43
32
VRegF2
3.0
-- +
+ -
GndReg2
VBATT --
44
IN1
0.8
44
33
VReg1
3.0
+ 33
GndReg1
45
GndL1
0.0
45
34
GndReg1
0.0 46 GndTx 0.0
POn 35 CMOS INPUT
35
-- +
47
OUT1
2.2
47
36 -- 48
36
VBATT
3.0
+
48
VCCL1
3.0
SR00163
Figure 29. Pin Functions (continued) 1997 May 22 23
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
1997 May 22
24
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
NOTES
1997 May 22
25
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1997 May 22 26

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